1. Field
Example embodiments relate to a storage device, for example, to a device and a method for manufacturing a non-volatile and electrically erasable semiconductor memory device, for example, a flash memory.
2. Description of the Related Art
Non-volatile memory retains information stored in its memory cells even when no power is supplied. Examples include mask ROM, EPROM, and EEPROM.
Non-volatile memory is widely used in various electronic products, for example, personal computers, personal digital assistants (PDAs), cellular phones, digital still cameras, digital video cameras, video game players, memory cards, and other electronic devices.
Memory cards types may include multimedia cards (MMC), secure digital (SD) cards, compact flash cards, memory sticks, smart media cards, and extreme digital (xD) picture cards.
Among non-volatile memory devices, a flash memory is widely used. Flash memory may be divided into a Not-OR (NOR) type and a Not-AND (NAND) type based on a connection structure of cells and bit lines. Because a read speed is faster and a write operation is slower, a NOR-type flash memory may be used as a code memory. Because a write speed is faster and a price per unit area is lower, a NAND-type flash memory may be used as a mass storage device. In order to write data in a flash memory, an erase operation is performed first, and the flash memory may have such a characteristic that an erase unit is larger than a write unit.
Program and erase operations are fundamental operations of a NAND device and are illustrated in FIGS. 1a and 1b, respectively. As shown in FIGS. 1a and 1b, a high electric field may be generated between a floating gate and a channel region. As charge moves through the tunneling oxide in one direction or the other, the threshold voltage (Vth) of the memory cell is changed
A read operation is also a fundamental operation of a NAND device. As shown in FIG. 1c, a control gate and a substrate are connected to ground. If a cell is a programmed cell, (Vth>0), the cell is off and the data value is 0. If a cell is an erased cell, (Vth<0), the cell is on and the data value is 1.
FIG. 2a illustrates a schematic and plan view of conventional NAND flash memory cells, including a string select line (SSL), a ground select line (GSL), a common source line (CSL), direct contacts (DC), a plurality of word lines (WL), a plurality of bit lines (BL), a charge storage layer (SA), active regions 113, and isolation regions 115.
FIG. 2b illustrates a vertical view of conventional NAND flash memory cells in a bit line (BL) direction and in a word line (WL) direction. The conventional NAND flash memory cells may include a tunnel insulating layer, a charge storage layer, a blocking layer, and/or a control gate layer. The charge storage layer may be floating gate layer. Floating gate interference may be defined as a Vth shift of a cell proportional to a Vth change of adjacent cells. The charge storage layer may be also be a charge trap layer.
FIG. 2c illustrates a vertical view of a conventional flash memory cell in the WL direction and FIG. 2d illustrates a cross-sectional view of line A-A′ in FIG. 2c. As shown, a conventional flash memory cell may include a substrate 11, active regions 13, isolation regions 15, a tunnel insulation layer 31, a floating gate 32, a blocking insulation layer 34, and a control gate 35.
As the size of memory cells is further reduced, a distance between floating gates 32 becomes shorter. The shorter the distance of the floating gates 32 becomes, the larger parasitic capacitances (C) become. Also, because boundaries of adjacent floating gates 32 may face each other (as shown in FIG. 2d), the parasitic capacitances (C) may be increased.